./goblint --conf conf/svcomp-validate.json --witness.yaml.unassume /mnt/goblint-svcomp/sv-comp/svcomp24-witnesses/results-verified/cpachecker.2023-11-29_00-03-15.files/SV-COMP24_unreach-call/verisec_OpenSER_cases1_stripFullBoth_arr.yml/witness.yml --witness.yaml.validate /mnt/goblint-svcomp/sv-comp/svcomp24-witnesses/results-verified/cpachecker.2023-11-29_00-03-15.files/SV-COMP24_unreach-call/verisec_OpenSER_cases1_stripFullBoth_arr.yml/witness.yml --sets ana.specification /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/properties/unreach-call.prp --sets exp.architecture 32bit /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i


--------------------------------------------------------------------------------


[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:67:7-67:66 with factor 25
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:70:7-70:67 with factor 25
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:3-89:3 with factor 8
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:10:5-12:5 with factor 12
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:21:9-27:9 with factor 4
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:40:3-45:3 with factor 6
[Info] no thread creation -> disabling thread analyses "race, deadlock, maylocks, symb_locks, thread, threadid, threadJoins, threadreturn, mhp, region"
[Info] Enabled congruence domain.
[Info] Enabled octagon domain ONLY for:
[Info] abort, __assert_fail, i, count, tmp, key, a, count, j, k, size, i, i___0, j___0, a, top, expression, i, j, start, i, str, dest, src, n, tmp, cond
[Info] Enabled widening thresholds
[Info] SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
[Info][Witness] cannot unassume entry of type violation_sequence
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:67:59-67:66)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:79:7-79:18)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:64:5-64:8)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:68:30-68:37)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 31
  dead: 0
  total lines: 31
[Warning][Deadcode][CWE-570] condition '0' is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:12:73-12:74)
[Warning][Deadcode][CWE-570] condition '! str' is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:62:7-62:11)
[Warning][Deadcode][CWE-571] condition 'i < 7' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Warning][Deadcode][CWE-571] condition 'i < 7' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Warning][Deadcode][CWE-571] condition 'i < 7' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Warning][Deadcode][CWE-571] condition 'i < 7' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Warning][Deadcode][CWE-571] condition 'i < 7' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Warning][Deadcode][CWE-571] condition 'i < 7' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Warning][Deadcode][CWE-571] condition 'i < 7' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Warning][Deadcode][CWE-570] condition 'i < 7' (possibly inserted by CIL) is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/loops/verisec_OpenSER_cases1_stripFullBoth_arr.i:87:7-87:38)
[Info][Witness] witness validation summary:
  confirmed: 0
  unconfirmed: 0
  refuted: 0
  error: 0
  unchecked: 0
  unsupported: 0
  disabled: 0
  total validation entries: 0
SV-COMP result: unknown
