./goblint --conf conf/svcomp.json --sets ana.specification /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/properties/no-overflow.prp --sets exp.architecture 32bit /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i


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[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:34:5-37:5 with factor 8
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:38:5-47:5 with factor 3
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:10:5-12:5 with factor 12
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:21:9-27:9 with factor 4
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:40:3-45:3 with factor 6
[Info] Setting "ana.int.interval" to true
[Info] no thread creation -> disabling thread analyses "race, deadlock, maylocks, symb_locks, thread, threadid, threadJoins, threadreturn, mhp, region, pthreadMutexType"
[Info] Enabled congruence domain.
[Info] Enabled octagon domain ONLY for:
[Info] counter, __VERIFIER_assert, i, count, tmp, key, a, count, j, k, size, i, i___0, j___0, a, top, expression, b, r, tmp, A, B, tmp___0, q, cond, cond
[Info] Enabled widening thresholds
[Info] SV-COMP specification: CHECK( init(main()), LTL(G ! overflow) )
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:48:5-48:38)
[Warning][Deadcode] Function 'assume_abort_if_not' is uncalled: 2 LLoC (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:15:1-17:1)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 25
  dead: 2 (2 in uncalled functions)
  total lines: 27
[Warning][Deadcode][CWE-570] condition '0' is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:12:73-12:74)
[Warning][Deadcode][CWE-570] condition 'tmp___0 < 2' (possibly inserted by CIL) is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:38:12-38:23)
[Warning][Deadcode][CWE-571] condition 'tmp < 2' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:34:12-34:23)
[Warning][Deadcode][CWE-571] condition 'tmp < 2' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:34:12-34:23)
[Warning][Deadcode][CWE-570] condition 'tmp < 2' (possibly inserted by CIL) is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/divbin2_unwindbound2.i:34:12-34:23)
SV-COMP result: true
[Info][Witness] witness generation summary:
  total generation entries: 1
