./goblint --conf conf/svcomp.json --sets ana.specification /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/properties/no-overflow.prp --sets exp.architecture 32bit /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c


--------------------------------------------------------------------------------


[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:10:5-12:5 with factor 12
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:21:9-27:9 with factor 4
[Info] unrolling loop at lib/libc/stub/src/stdlib.c:40:3-45:3 with factor 6
[Info] Setting "ana.int.interval" to true
[Info] function main uses mod, enable congruence domain recursively for:
[Info]   "down":
[Info]     __VERIFIER_nondet_int
[Info]     assume_abort_if_not
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     func_to_recursive_line_33_to_42_0
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     func_to_recursive_line_33_to_42_0
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     func_to_recursive_line_33_to_42_0
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     func_to_recursive_line_33_to_42_0
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     func_to_recursive_line_33_to_42_0
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     func_to_recursive_line_33_to_42_0
[Info]     __VERIFIER_assert
[Info]     func_to_recursive_line_33_to_42_0
[Info]   "up":
[Info] function func_to_recursive_line_33_to_42_0 is recursive, disable interval and interval_set contexts
[Info] no thread creation -> disabling thread analyses "race, deadlock, maylocks, symb_locks, thread, threadid, threadJoins, threadreturn, mhp, region, pthreadMutexType"
[Info] Enabled congruence domain.
[Info] Enabled widening thresholds
[Info] Enabled octagon domain ONLY for:
[Info] abort, assume_abort_if_not, i, count, tmp, key, a, count, j, k, size, i, i___0, j___0, a, top, expression, A, u, v, r, v, u, A, cond, cond
[Info] SV-COMP specification: CHECK( init(main()), LTL(G ! overflow) )
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:53:7-53:110)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:53:7-53:110)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:53:7-53:110)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:68:9-68:25)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:69:9-69:22)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:64:9-64:22)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:94:3-94:90)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:94:3-94:90)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:94:3-94:90)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 34
  dead: 0
  total lines: 34
[Warning][Deadcode][CWE-571] condition '1' is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/recursified_nla-digbench/recursified_fermat2-ll.c:50:7-50:8)
SV-COMP result: unknown
[Info][Witness] witness generation summary:
  total generation entries: 1
