./goblint --conf conf/svcomp.json --sets ana.specification /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/properties/no-overflow.prp --sets exp.architecture 32bit /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c


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[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:36:3-87:3 with factor 2
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:89:3-92:3 with factor 2
[Info] Setting "ana.int.interval" to true
[Info] function main uses mod, enable congruence domain recursively for:
[Info]   "down":
[Info]     assume_abort_if_not
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     __VERIFIER_nondet_int
[Info]     ReadFromPort
[Info]     __VERIFIER_nondet_int
[Info]   "up":
[Info] no thread creation -> disabling thread analyses "race, deadlock, maylocks, symb_locks, thread, threadid, threadJoins, threadreturn, mhp, region, pthreadMutexType"
[Info] Enabled congruence domain.
[Info] Enabled widening thresholds
[Info] Enabled octagon domain ONLY for:
[Info] SIZE, ReadFromPort, i, count, tmp, key, a, count, i, j, i___0, j___0, k, size, r, top, expression, DEFAULTVAL, value, i, FIXEDVAL, x, tmp, cond, cond
[Info] SV-COMP specification: CHECK( init(main()), LTL(G ! overflow) )
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:29:7-29:36)
[Warning][Deadcode] Function 'reach_error' is uncalled: 1 LLoC (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:3:1-3:70)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 40
  dead: 1 (1 in uncalled functions)
  total lines: 41
[Warning][Deadcode][CWE-570] condition '! cond' is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:6:6-6:11)
[Warning][Deadcode][CWE-570] condition '! cond' is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:8:39-8:46)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:89:7-89:29)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pnr5.c:89:7-89:29)
SV-COMP result: true
[Info][Witness] witness generation summary:
  total generation entries: 1
