./goblint --conf conf/svcomp.json --sets ana.specification /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/properties/no-overflow.prp --sets exp.architecture 32bit /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c


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[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c:46:2-58:2 with factor 2
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c:37:5-61:5 with factor 2
[Info] Setting "ana.int.interval" to true
[Info] no thread creation -> disabling thread analyses "race, deadlock, maylocks, symb_locks, thread, threadid, threadJoins, threadreturn, mhp, region, pthreadMutexType"
[Info] Enabled congruence domain.
[Info] Enabled widening thresholds
[Info] Enabled octagon domain ONLY for:
[Info] __VERIFIER_assert, counter, i, count, tmp, key, a, count, i, j, i___0, j___0, k, size, r, top, expression, r, b, x, tmp, a, y, tmp___0, q, cond, cond
[Info] SV-COMP specification: CHECK( init(main()), LTL(G ! overflow) )
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 35
  dead: 0
  total lines: 35
[Warning][Deadcode][CWE-570] condition 'tmp < 5' (possibly inserted by CIL) is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c:46:9-46:20)
[Warning][Deadcode][CWE-571] condition 'tmp___0 < 5' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c:37:12-37:23)
[Warning][Deadcode][CWE-571] condition 'tmp < 5' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c:46:9-46:20)
[Warning][Deadcode][CWE-570] condition 'tmp < 5' (possibly inserted by CIL) is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c:46:9-46:20)
[Warning][Deadcode][CWE-571] condition 'tmp < 5' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/nla-digbench-scaling/cohendiv-ll_unwindbound5.c:46:9-46:20)
SV-COMP result: true
[Info][Witness] witness generation summary:
  total generation entries: 1
