./goblint --conf conf/svcomp.json --sets ana.specification /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/properties/no-overflow.prp --sets exp.architecture 32bit /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pr4.c


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[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pr4.c:29:3-66:3 with factor 2
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pr4.c:68:3-71:3 with factor 2
[Info] Setting "ana.int.interval" to true
[Info] function main uses mod, enable congruence domain recursively for:
[Info]   "down":
[Info]     assume_abort_if_not
[Info]     __VERIFIER_assert
[Info]     reach_error
[Info]     __VERIFIER_nondet_int
[Info]   "up":
[Info] no thread creation -> disabling thread analyses "race, deadlock, maylocks, symb_locks, thread, threadid, threadJoins, threadreturn, mhp, region, pthreadMutexType"
[Info] Enabled congruence domain.
[Info] Enabled widening thresholds
[Info] Enabled octagon domain ONLY for:
[Info] CELLCOUNT, abort, i, count, tmp, key, a, count, i, j, i___0, j___0, k, size, r, top, expression, MINVAL, i, volArray, CCCELVOL4, CCCELVOL3, CCCELVOL2, CCCELVOL1, tmp, cond, cond
[Info] SV-COMP specification: CHECK( init(main()), LTL(G ! overflow) )
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pr4.c:29:6-29:35)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 32
  dead: 0
  total lines: 32
[Warning][Deadcode][CWE-571] condition 'i < CELLCOUNT' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pr4.c:68:6-68:32)
[Warning][Deadcode][CWE-571] condition 'i < CELLCOUNT' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pr4.c:68:6-68:32)
[Warning][Deadcode][CWE-570] condition '! cond' is always false (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/pr4.c:6:6-6:11)
SV-COMP result: unknown
[Info][Witness] witness generation summary:
  total generation entries: 1
