./goblint --conf conf/svcomp.json --sets ana.specification /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/properties/no-overflow.prp --sets exp.architecture 32bit /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c


--------------------------------------------------------------------------------


[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[0;33m[Warning] --sets is deprecated, use --set instead.[0;0;00m
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:29:3-33:3 with factor 2
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:36:3-40:3 with factor 2
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:43:3-48:3 with factor 2
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:51:3-56:3 with factor 2
[Info] unrolling loop at /mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:59:3-63:3 with factor 2
[Info] Setting "ana.int.interval" to true
[Info] no thread creation -> disabling thread analyses "race, deadlock, maylocks, symb_locks, thread, threadid, threadJoins, threadreturn, mhp, region, pthreadMutexType"
[Info] Enabled congruence domain.
[Info] Enabled widening thresholds
[Info] Enabled octagon domain ONLY for:
[Info] SIZE, MAX, i, count, tmp, key, a, count, i, j, i___0, j___0, k, size, r, top, expression, i, tmp, cond, cond
[Info] SV-COMP specification: CHECK( init(main()), LTL(G ! overflow) )
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:24:7-24:36)
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:25:7-25:36)
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:26:7-26:41)
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:27:7-27:41)
[Warning][Deadcode] Function 'assume_abort_if_not' is uncalled: 2 LLoC (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:6:1-8:1)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 27
  dead: 2 (2 in uncalled functions)
  total lines: 29
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:43:6-43:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:43:6-43:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:51:6-51:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:51:6-51:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:59:6-59:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:59:6-59:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:29:6-29:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:29:6-29:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:36:6-36:23)
[Warning][Deadcode][CWE-571] condition 'i < SIZE' (possibly inserted by CIL) is always true (/mnt/goblint-svcomp/benchexec/sv-benchmarks/c/array-tiling/revcpyswp2.c:36:6-36:23)
SV-COMP result: true
[Info][Witness] witness generation summary:
  total generation entries: 1
