/mnt/thread-witnesses/replication/bench/thread-witnesses/st-cross/../../../ourtool/goblint --conf conf/svcomp-yaml.json --enable dbg.timing.enabled --set 'ana.activated[+]' apron --set ana.apron.domain polyhedra --enable witness.enabled --sets ana.specification ../properties/unreach-call.prp --sets exp.architecture 32bit ../plain/cohendiv-ll.c


--------------------------------------------------------------------------------


--sets is deprecated, use --set instead.
--sets is deprecated, use --set instead.
SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:50:10-50:23)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:53:6-53:39)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/cohendiv-ll.c:55:6-55:15)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:56:6-56:15)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:37:2-37:29)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:38:2-38:33)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:46:6-46:33)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:47:6-47:37)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/cohendiv-ll.c:59:2-59:11)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (../plain/cohendiv-ll.c:62:5-62:36)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 35
  dead: 0
  total lines: 35
[Warning][Deadcode][CWE-571] condition '1' (possibly inserted by CIL) is always true (../plain/cohendiv-ll.c:45:9-45:10)
[Warning][Deadcode][CWE-571] condition '1' (possibly inserted by CIL) is always true (../plain/cohendiv-ll.c:36:12-36:13)
SV-COMP result: unknown
[Info][Witness] witness generation summary:
  total generation entries: 128

vars = 98    evals = 341    narrow_reuses = 8

Timings:
                                  cputime   walltime   allocated   count
Default                            0.221s     0.253s    203.52MB      1×
  preprocess                         0.026s     0.057s      0.01MB      1×
  FrontC                             0.007s     0.007s      4.14MB      4×
  Cabs2cil                           0.006s     0.006s      4.77MB      4×
  mergeCIL                           0.004s     0.004s      3.34MB      1×
  analysis                           0.173s     0.173s    186.44MB      1×
    createCFG                          0.001s     0.001s      0.64MB      1×
      handle                             0.001s     0.001s      0.10MB     34×
      iter_connect                       0.001s     0.001s      0.42MB     34×
        computeSCCs                        0.001s     0.001s      0.25MB     35×
    global_inits                       0.001s     0.001s      0.05MB      1×
    solving                            0.150s     0.150s    146.55MB      1×
      S.Dom.equal                        0.001s     0.001s      0.12MB    349×
      cheap_full_reach                   0.001s     0.001s      0.03MB      1×
      postsolver                         0.017s     0.017s     16.64MB      1×
        postsolver_iter                    0.017s     0.017s     16.50MB      1×
    warn_global                        0.001s     0.001s      0.64MB      1×
    witness                            0.012s     0.012s     25.69MB      1×
      determine                          0.001s     0.001s      0.17MB      1×
      write                              0.012s     0.012s     25.53MB      1×
    result output                      0.001s     0.001s      0.01MB      1×
