/mnt/thread-witnesses/replication/bench/thread-witnesses/st-cross/../../../ourtool/goblint --conf conf/svcomp-yaml.json --enable dbg.timing.enabled --set 'ana.activated[+]' apron --set ana.apron.domain polyhedra --enable witness.enabled --sets ana.specification ../properties/unreach-call.prp --sets exp.architecture 32bit ../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i


--------------------------------------------------------------------------------


--sets is deprecated, use --set instead.
--sets is deprecated, use --set instead.
SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:67:59-67:66)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:73:13-73:25)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:73:13-73:25)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:82:7-82:18)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:64:5-64:8)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:68:30-68:37)
[Warning][Deadcode] Function 'reach_error' is uncalled: 1 LLoC (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:12:1-12:193)
[Warning][Deadcode] Function '__VERIFIER_assert' has dead code:
  on line 16 (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:16-16)
[Warning][Deadcode] Logical lines of code (LLoC) summary:
  live: 31
  dead: 2 (1 in uncalled functions)
  total lines: 33
[Warning][Deadcode][CWE-570] condition '! cond' is always false (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:15:7-15:14)
[Warning][Deadcode][CWE-570] condition '! str' is always false (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:62:7-62:11)
SV-COMP result: true
[Info][Witness] witness generation summary:
  total generation entries: 125

vars = 84    evals = 206    narrow_reuses = 26

Timings:
                                  cputime   walltime   allocated   count
Default                            0.252s     0.268s    213.06MB      1×
  preprocess                         0.028s     0.043s      0.01MB      1×
  FrontC                             0.006s     0.006s      4.45MB      4×
  Cabs2cil                           0.006s     0.006s      5.24MB      4×
  mergeCIL                           0.003s     0.003s      3.45MB      1×
  analysis                           0.205s     0.205s    195.05MB      1×
    createCFG                          0.001s     0.001s      0.69MB      1×
      handle                             0.001s     0.001s      0.12MB     35×
      iter_connect                       0.001s     0.001s      0.45MB     35×
        computeSCCs                        0.001s     0.001s      0.26MB     36×
    global_inits                       0.001s     0.001s      0.05MB      1×
    solving                            0.183s     0.183s    158.48MB      1×
      S.Dom.equal                        0.001s     0.001s      0.08MB    232×
      cheap_full_reach                   0.001s     0.001s      0.03MB      1×
      postsolver                         0.028s     0.028s     26.80MB      1×
        postsolver_iter                    0.028s     0.028s     26.63MB      1×
    warn_global                        0.001s     0.001s      0.99MB      1×
    witness                            0.011s     0.011s     22.56MB      1×
      determine                          0.001s     0.001s      0.14MB      1×
      write                              0.011s     0.011s     22.43MB      1×
    result output                      0.001s     0.001s      0.01MB      1×
