/mnt/thread-witnesses/replication/bench/thread-witnesses/st-cross/../../../ourtool/goblint --conf conf/svcomp-yaml.json --enable dbg.timing.enabled --set 'ana.activated[+]' apron --set ana.apron.domain polyhedra --enable witness.enabled --sets ana.specification ../properties/unreach-call.prp --sets exp.architecture 32bit ../plain/divbin_unwindbound5.i


--------------------------------------------------------------------------------


--sets is deprecated, use --set instead.
--sets is deprecated, use --set instead.
SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (../plain/divbin_unwindbound5.i:38:9-38:18)
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (../plain/divbin_unwindbound5.i:41:9-41:42)
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (../plain/divbin_unwindbound5.i:43:9-43:18)
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (../plain/divbin_unwindbound5.i:46:13-46:22)
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (../plain/divbin_unwindbound5.i:47:13-47:22)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/divbin_unwindbound5.i:40:12-40:23)
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (../plain/divbin_unwindbound5.i:50:5-50:38)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 30
  dead: 0
  total lines: 30
[Warning][Deadcode][CWE-570] condition '0' (possibly inserted by CIL) is always false (../plain/divbin_unwindbound5.i:12:73-12:74)
SV-COMP result: unknown
[Info][Witness] witness generation summary:
  total generation entries: 139

vars = 93    evals = 155    narrow_reuses = 2

Timings:
                                  cputime   walltime   allocated   count
Default                            0.209s     0.209s    132.63MB      1×
  preprocess                         0.024s     0.023s      0.01MB      1×
  FrontC                             0.005s     0.005s      4.18MB      4×
  Cabs2cil                           0.005s     0.005s      4.82MB      4×
  mergeCIL                           0.003s     0.003s      3.35MB      1×
  analysis                           0.167s     0.167s    115.46MB      1×
    createCFG                          0.001s     0.001s      0.65MB      1×
      handle                             0.001s     0.001s      0.10MB     34×
      iter_connect                       0.001s     0.001s      0.43MB     34×
        computeSCCs                        0.001s     0.001s      0.25MB     35×
    global_inits                       0.001s     0.001s      0.17MB      1×
    solving                            0.138s     0.138s     72.28MB      1×
      S.Dom.equal                        0.001s     0.001s      0.06MB    157×
      cheap_full_reach                   0.001s     0.001s      0.03MB      1×
      postsolver                         0.030s     0.030s     17.30MB      1×
        postsolver_iter                    0.030s     0.030s     17.15MB      1×
    warn_global                        0.001s     0.001s      0.98MB      1×
    witness                            0.015s     0.015s     26.29MB      1×
      determine                          0.001s     0.001s      0.17MB      1×
      write                              0.015s     0.015s     26.12MB      1×
    result output                      0.001s     0.001s      0.01MB      1×
