/mnt/thread-witnesses/replication/bench/thread-witnesses/st-cross/../../../ourtool/goblint --conf conf/svcomp-yaml-validate.json --enable dbg.timing.enabled --set 'ana.activated[+]' apron --set ana.apron.domain polyhedra --witness.yaml.unassume cbmc/veris.c_OpenSER_cases1_stripFullBoth_arr.yml.witness.yml --witness.yaml.validate cbmc/veris.c_OpenSER_cases1_stripFullBoth_arr.yml.witness.yml --sets ana.specification ../properties/unreach-call.prp --sets exp.architecture 32bit ../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i


--------------------------------------------------------------------------------


--sets is deprecated, use --set instead.
--sets is deprecated, use --set instead.
SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
[Warning][Witness] couldn't locate invariant: i == (0) || i == (1) || i == (2) || i == (3) || i == (4) || i == (5) || i == (6) (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:93:3)
[Warning][Witness] couldn't locate invariant: i == (0) || i == (1) || i == (2) || i == (3) || i == (4) || i == (5) || i == (6) (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:91:5)
[Error][Witness] CIL couldn't parse invariant: start == (1) || start == (2) || start == (0) || j == (-1) || dest == str2 (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85:3)
[Info][Witness] invariant has undefined variables or side effects: start == (1) || start == (2) || start == (0) || j == (-1) || dest == str2 (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85:3)
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable start.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable start.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable start.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable j.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable dest.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable str2.
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:67:59-67:66)
[Info][Witness] unassume invariant: ((start == 0 || i == -1) && start == 0) && ((start == 0 || i == -1) || j == -1) (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:62:7-62:11)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:73:13-73:25)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:73:13-73:25)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:82:7-82:18)
[Info][Witness] unassume invariant: ((start == 0 || i == -1) && start == 0) && ((start == 0 || i == -1) || j == -1) (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:84:12-84:24)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:64:5-64:8)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:68:30-68:37)
[Warning][Deadcode] Function 'reach_error' is uncalled: 1 LLoC (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:12:1-12:193)
[Warning][Deadcode] Function '__VERIFIER_assert' has dead code:
  on line 16 (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:16-16)
[Warning][Deadcode] Logical lines of code (LLoC) summary:
  live: 31
  dead: 2 (1 in uncalled functions)
  total lines: 33
[Warning][Deadcode][CWE-570] condition '! cond' is always false (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:15:7-15:14)
[Warning][Deadcode][CWE-570] condition '! str' is always false (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:62:7-62:11)
[Warning][Witness] invariant unconfirmed: start == (0) || i == (-1) || j == (-1) (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:61:3)
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable start.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable start.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable start.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable j.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable dest.
../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:85: Error: Cannot resolve variable str2.
[Warning][Witness] invariant unconfirmed: start == (0) (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:60:3)
[Warning][Witness] invariant unconfirmed: start == (0) || i == (-1) (../plain/veris.c_OpenSER_cases1_stripFullBoth_arr.i:60:3)
[Info][Witness] witness validation summary:
  confirmed: 0
  unconfirmed: 3
  refuted: 0
  error: 3
  unchecked: 0
  unsupported: 0
  disabled: 0
  total validation entries: 6
SV-COMP result: unknown

vars = 84    evals = 206    narrow_reuses = 26

Timings:
                                  cputime   walltime   allocated   count
Default                            0.232s     0.232s    163.67MB      1×
  preprocess                         0.025s     0.024s      0.01MB      1×
  FrontC                             0.005s     0.005s      4.45MB      4×
  Cabs2cil                           0.006s     0.006s      5.24MB      4×
  mergeCIL                           0.003s     0.003s      3.45MB      1×
  analysis                           0.189s     0.189s    145.48MB      1×
    createCFG                          0.001s     0.001s      0.69MB      1×
      handle                             0.001s     0.001s      0.12MB     35×
      iter_connect                       0.001s     0.001s      0.45MB     35×
        computeSCCs                        0.001s     0.001s      0.26MB     36×
    FrontC                             0.001s     0.001s      0.09MB      8×
    Cabs2cil                           0.002s     0.002s      0.88MB      8×
    global_inits                       0.001s     0.001s      0.05MB      1×
    solving                            0.177s     0.177s    135.09MB      1×
      S.Dom.equal                        0.001s     0.001s      0.08MB    232×
      base unassume                      0.003s     0.003s      4.54MB     19×
      cheap_full_reach                   0.001s     0.001s      0.03MB      1×
      postsolver                         0.027s     0.027s     21.73MB      1×
        postsolver_iter                    0.027s     0.027s     21.66MB      1×
    warn_global                        0.001s     0.001s      0.29MB      1×
    witness                            0.001s     0.001s      0.01MB      1×
    result output                      0.001s     0.001s      0.01MB      1×
