./goblint --conf conf/svcomp-yaml-validate.json --enable dbg.timing.enabled --set 'ana.activated[+]' apron --set ana.apron.domain polyhedra --witness.yaml.unassume /mnt/thread-witnesses/replication/bench/thread-witnesses/st-lit/../../../results/st-lit-location/convert-tmp.2023-02-16_10-47-42.files/cpachecker/mine-tutorial-ex4.7.yml/witness.yml --witness.yaml.validate /mnt/thread-witnesses/replication/bench/thread-witnesses/st-lit/../../../results/st-lit-location/convert-tmp.2023-02-16_10-47-42.files/cpachecker/mine-tutorial-ex4.7.yml/witness.yml --sets ana.specification /mnt/thread-witnesses/replication/bench/thread-witnesses/st-lit/properties/unreach-call.prp --sets exp.architecture 64bit /mnt/thread-witnesses/replication/bench/thread-witnesses/st-lit/prec/mine-tutorial-ex4.7.i


--------------------------------------------------------------------------------


--sets is deprecated, use --set instead.
--sets is deprecated, use --set instead.
SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
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!(x == (5)) && !(x == (7)) && !(x == (27)) && !(x == (6)) && !(x == (38)) && !(x == (31)) && !(x == (40)) && !(x == (32)) && !(x == (35)) && !(x == (28)) && !(x == (29)) && !(x == (19)) && !(x == (3)) && !(x == (25)) && !(x == (20)) && !(x == (12)) && !(x == (10)) && !(x == (11)) && !(x == (24)) && !(x == (36)) && !(x == (14)) && !(x == (17)) && !(x == (18)) && !(x == (0)) && !(x == (9)) && !(x == (15)) && !(x == (22)) && !(x == (26)) && !(x == (33)) && !(x == (13)) && !(x == (1)) && !(x == (4)) && !(x == (39)) && !(x == (16)) && !(x == (8)) && !(x == (21)) && !(x == (34)) && x == (2)) (/mnt/thread-witnesses/replication/bench/thread-witnesses/st-lit/prec/mine-tutorial-ex4.7.i:18:5)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/thread-witnesses/replication/bench/thread-witnesses/st-lit/prec/mine-tutorial-ex4.7.i:21:7-21:10)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 13
  dead: 0
  total lines: 13
[Warning][Deadcode][CWE-570] condition '0' (possibly inserted by CIL) is always false (/mnt/thread-witnesses/replication/bench/thread-witnesses/st-lit/prec/mine-tutorial-ex4.7.i:12:73-12:74)
[Info][Witness] witness validation summary:
  confirmed: 0
  unconfirmed: 0
  refuted: 0
  error: 2
  unchecked: 0
  unsupported: 0
  disabled: 0
  total validation entries: 2
SV-COMP result: unknown

vars = 52    evals = 108    narrow_reuses = 1

Timings:
                                  cputime   walltime   allocated   count
Default                            0.093s     0.093s     62.75MB      1×
  preprocess                         0.024s     0.023s      0.01MB      1×
  FrontC                             0.005s     0.005s      4.11MB      4×
  Cabs2cil                           0.005s     0.005s      4.71MB      4×
  mergeCIL                           0.003s     0.003s      3.34MB      1×
  analysis                           0.052s     0.052s     45.64MB      1×
    createCFG                          0.001s     0.001s      0.59MB      1×
      handle                             0.001s     0.001s      0.09MB     33×
      iter_connect                       0.001s     0.001s      0.40MB     33×
        computeSCCs                        0.001s     0.001s      0.23MB     34×
    global_inits                       0.001s     0.001s      0.05MB      1×
    solving                            0.042s     0.043s     33.58MB      1×
      S.Dom.equal                        0.001s     0.001s      0.04MB    109×
      cheap_full_reach                   0.001s     0.001s      0.02MB      1×
      postsolver                         0.008s     0.008s      6.92MB      1×
        postsolver_iter                    0.008s     0.008s      6.87MB      1×
    warn_global                        0.001s     0.001s      0.11MB      1×
    witness                            0.001s     0.001s      0.13MB      1×
      determine                          0.001s     0.001s      0.12MB      1×
    result output                      0.001s     0.001s      0.01MB      1×
