./goblint --conf conf/svcomp-yaml-validate.json --enable dbg.timing.enabled --set 'ana.activated[+]' apron --set ana.apron.domain polyhedra --witness.yaml.unassume /mnt/thread-witnesses/replication/bench/thread-witnesses/st-same/../../../results/st-same/ourtool.2023-01-27_15-24-18.files/loop-head/lcm2.yml/witness.yml --witness.yaml.validate /mnt/thread-witnesses/replication/bench/thread-witnesses/st-same/../../../results/st-same/ourtool.2023-01-27_15-24-18.files/loop-head/lcm2.yml/witness.yml --enable witness.invariant.loop-head --disable witness.invariant.other --disable witness.invariant.accessed --sets ana.specification /mnt/thread-witnesses/replication/sv-benchmarks/c/properties/unreach-call.prp --sets exp.architecture 32bit /mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c


--------------------------------------------------------------------------------


--sets is deprecated, use --set instead.
--sets is deprecated, use --set instead.
SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c:36:9-36:46)
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c:45:13-45:22)
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c:46:13-46:22)
[Warning][Integer > Overflow][CWE-191] Unsigned integer underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c:42:13-42:22)
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c:43:13-43:22)
[Warning][Integer > Overflow][CWE-190] Unsigned integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c:50:5-50:42)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 30
  dead: 0
  total lines: 30
[Warning][Deadcode][CWE-571] condition '1' (possibly inserted by CIL) is always true (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/lcm2.c:35:12-35:13)
[Info][Witness] witness validation summary:
  confirmed: 0
  unconfirmed: 0
  refuted: 0
  error: 0
  unchecked: 0
  unsupported: 0
  disabled: 0
  total validation entries: 0
SV-COMP result: unknown

vars = 58    evals = 136    narrow_reuses = 2

Timings:
                                  cputime   walltime   allocated   count
Default                            0.165s     0.166s     76.29MB      1×
  preprocess                         0.027s     0.026s      0.01MB      1×
  FrontC                             0.004s     0.005s      4.13MB      4×
  Cabs2cil                           0.007s     0.007s      4.75MB      4×
  mergeCIL                           0.004s     0.004s      3.34MB      1×
  analysis                           0.119s     0.119s     58.56MB      1×
    createCFG                          0.001s     0.001s      0.63MB      1×
      handle                             0.001s     0.001s      0.10MB     34×
      iter_connect                       0.001s     0.001s      0.42MB     34×
        computeSCCs                        0.001s     0.001s      0.25MB     35×
    global_inits                       0.001s     0.001s      0.05MB      1×
    solving                            0.115s     0.116s     53.96MB      1×
      S.Dom.equal                        0.001s     0.001s      0.05MB    138×
      cheap_full_reach                   0.001s     0.001s      0.03MB      1×
      postsolver                         0.025s     0.025s     10.91MB      1×
        postsolver_iter                    0.025s     0.025s     10.86MB      1×
    warn_global                        0.001s     0.001s      0.11MB      1×
    witness                            0.001s     0.001s      0.16MB      1×
      determine                          0.001s     0.001s      0.16MB      1×
    result output                      0.001s     0.001s      0.01MB      1×
