./goblint --conf conf/svcomp-yaml.json --enable dbg.timing.enabled --set 'ana.activated[+]' apron --set ana.apron.domain polyhedra --enable witness.invariant.loop-head --disable witness.invariant.other --disable witness.invariant.accessed --sets ana.specification /mnt/thread-witnesses/replication/sv-benchmarks/c/properties/unreach-call.prp --sets exp.architecture 32bit /mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c


--------------------------------------------------------------------------------


--sets is deprecated, use --set instead.
--sets is deprecated, use --set instead.
SV-COMP specification: CHECK( init(main()), LTL(G ! call(reach_error())) )
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:50:13-50:22)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:51:13-51:22)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:43:13-43:22)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:34:9-34:60)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:34:9-34:60)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:34:9-34:60)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:39:6-39:57)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:39:6-39:57)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:39:6-39:57)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:47:6-47:57)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:47:6-47:57)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:47:6-47:57)
[Warning][Integer > Overflow][CWE-190][CWE-191] Signed integer overflow and underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:55:5-55:66)
[Warning][Integer > Overflow][CWE-190] Signed integer overflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:55:5-55:66)
[Warning][Integer > Overflow][CWE-191] Signed integer underflow (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:55:5-55:66)
[Info][Deadcode] Logical lines of code (LLoC) summary:
  live: 32
  dead: 0
  total lines: 32
[Warning][Deadcode][CWE-571] condition '1' (possibly inserted by CIL) is always true (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:38:16-38:17)
[Warning][Deadcode][CWE-571] condition '1' (possibly inserted by CIL) is always true (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:46:16-46:17)
[Warning][Deadcode][CWE-571] condition '1' (possibly inserted by CIL) is always true (/mnt/thread-witnesses/replication/sv-benchmarks/c/nla-digbench/fermat1-ll.c:33:12-33:13)
SV-COMP result: unknown
[Info][Witness] witness generation summary:
  total generation entries: 17

vars = 68    evals = 258    narrow_reuses = 15

Timings:
                                  cputime   walltime   allocated   count
Default                            0.198s     0.198s    126.13MB      1×
  preprocess                         0.024s     0.023s      0.01MB      1×
  FrontC                             0.004s     0.004s      4.18MB      4×
  Cabs2cil                           0.006s     0.006s      4.86MB      4×
  mergeCIL                           0.003s     0.003s      3.35MB      1×
  analysis                           0.157s     0.157s    108.55MB      1×
    createCFG                          0.001s     0.001s      0.64MB      1×
      handle                             0.001s     0.001s      0.10MB     34×
      iter_connect                       0.001s     0.001s      0.42MB     34×
        computeSCCs                        0.001s     0.001s      0.24MB     35×
    global_inits                       0.001s     0.001s      0.05MB      1×
    solving                            0.151s     0.152s    102.55MB      1×
      S.Dom.equal                        0.001s     0.001s      0.10MB    273×
      cheap_full_reach                   0.001s     0.001s      0.03MB      1×
      postsolver                         0.018s     0.018s     13.29MB      1×
        postsolver_iter                    0.018s     0.018s     13.23MB      1×
    warn_global                        0.001s     0.001s      0.18MB      1×
    witness                            0.001s     0.001s      0.16MB      1×
      determine                          0.001s     0.001s      0.16MB      1×
    result output                      0.001s     0.001s      0.01MB      1×
